A conventional non-volatile memory cell includes a first terminal or a floating gate having high impedance and a second terminal or a MOS transistor having a control gate. Current electric memory circuits include thousands of cells that are integrated, with high packing rates, into a matrix shape in a semiconductor.
Because cells of a memory cell array are operated separately, each of the cells of a non-volatile memory chip needs to be able to receive programming or erasing signals. All of the cells are consequently required to have characteristics that lie within program operation and erasure operation minimum voltage margins. Different cells, however, have different threshold voltages for programming and erasing operations.
The ability to measure the distribution of threshold voltages (Vth) of (programmed and erased) memory cells is therefore very important to the fabricators and designers of memory devices. The density of threshold voltage distribution is a yardstick for determining whether memory arrangements are acceptable and whether state machines will smoothly perform their functions. To test the threshold voltage (Vth) of a memory cell, the gate voltage of a memory cell is supplied with a test voltage from the outside. In a memory circuit, the test voltage externally supplied to a cell terminal may be a program voltage.
FIG. 1 is a block diagram of a semiconductor memory device having a switching circuit 40 for testing the threshold voltage of a memory cell 20. As shown in FIG. 1, a semiconductor memory device includes a test pad 10, a memory cell array 20, a row decoder 30, a switching circuit 40, and a word line voltage generation circuit 50. The switching circuit 40 includes a PMOS transistor PM1, an NMOS transistor NM1, and an inverter INV1. During a test mode (when a test signal TE transitions to a high level), a test voltage from a test pad 10 is transferred to an output terminal 1. The test voltage is supplied to a gate of a selected cell 20 through a row decoder 30 (via a word line VwL). When the test voltage causes the gate of the selected cell 20 to start turning on, then that test (gate) voltage is the threshold voltage (Vth) of the selected memory cell 20.
When a test signal TE, applied to the word line voltage generation circuit 50, is disabled to a low level (i.e., during a program verify mode), a word line voltage is supplied to a word line voltage output terminal 1 from the word line voltage generation circuit 50. The word line voltage is then transferred to a selected word line through a row decoder 30. During a program mode (or read mode), the row decoder 30 receives a program voltage Vpgrn (or read voltage Vread) from a program (or read) voltage generation circuit (not shown). The row decoder 30 then transfers the program voltage Vpgm (or read voltage Vread) to the selected word line 1, while transferring a pass voltage Vpass to non-selected word lines.
FIG. 2 shows switching circuit 40 schematically and in a cross-sectional view. Referring now to FIGS. 1 and 2, the PMOS transistor PM1 and the NMOS transistor NM1 of the switching circuit 40 are formed as an N-well 62 and a P-well 64, respectively, in a P-type substrate 60. The N-well 62 is coupled to a low power supply voltage Vcc (e.g., 2.1V or less), and the P-well is coupled to a ground GND.
In the switching circuit 40 of a memory device having multi-bit memory cells 20, when a test signal TE is disabled (for example, during a program verify mode), a voltage of 0.4V, 1.6V, or 2.8V is supplied to the selected word line in a state of "10", "01", or "00", respectively. A voltage of 0.8V-1.0V, on the other hand, is supplied to a word line of a single-bit memory cell during program verify operation.
In operation, when the test signal TE is disabled, the PMOS transistor PM1 and the NMOS transistor NM1 of the switching circuit 40 are turned off. A voltage (2.2V in a state of "00") is supplied to the output terminal 1 of a word line voltage generation circuit 50, and a low power supply voltage of about 2.1V or less is supplied to the N-well 62. A PN diode D1 is consequently turned on between a source 66b (connected to V.sub.WL) and the well 62 of the PMOS transistor coupled to the word line voltage output terminal 1, so that leakage current flows. This leakage current makes it impossible to verify a normal program operation under these conditions.